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IZD1520U DOT MATRIX LIQUID CRYSTAL DISPLAY CONTROLLER & DRIVER
FEATURES
* CMOS LSI chips * Connection with CPU Can be directly coupled with 80-port or 68-port system * Available in chip form or in 100-pin plastic QFP * Pin-to-Pin Replacement for SED1520 Series * Many command set * Total 80 (segment+common) drive sets * Low power consumption - 30W maximum at 2kHz external clock * Power supply VDD - VSS : 2.4 to -7.0V VDD - V5 : 3.5 to -13.0V
DESCRIPTION The IZD1520 family of dot matrix LCD (Liquid Crystal Display) drivers are designed for the display of characters and graphics. The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM. The IZD1520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages. These features give the designer a flexible means of implementing small to medium size LCD displays for compact, low power systems. The IZD1520 which is able to drive two lines of twelve characters each. The IZD1521 which is able to drive 80 segments for extention. ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Soldering temperature time (10 sec max) Symbol VSS V5 V1, V2, V3, V4 VI VO PD Ta Tstg Tsol Value - 8.0 ~ 0.3 - 16.5 ~ 0.3 V5 ~ 0.3 VSS - 0.3 ~ 0.3 VSS - 0.3 ~ 0.3 250 - 10 ~ + 75 - 65 ~ + 150 260 Unit V V V V V mW
o o o
C C C
Notes: 1. 2.
All voltages are specified relative to VDD = 0V. The following relation must be always hold VDD V1 V2 V3 V4 V5. 3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional operating under these conditions is not implied.
1
IZD1520U
LINE-UP
Product Name IZD1520OA IZD1521OA IZD1520AA IZD1521AA Clock Frequency On-chip External 18kHz 18kHz 18kHz 2kHz 2kHz Applicable Driver Number of SEGMENT Drivers 61 80 61 80 Number of COMMON Drivers 16 0 16 0 Duty
IZ1520OA , IZ1521OA IZ1520OA IZ1520AA , IZ1521AA IZ1520AA
1/16, 1/32 1/8 ~ 1/32 1/16, 1/32 1/8 ~ 1/32
BLOCK DIAGRAM IZ1520AA
COM0 to COM15 SEG0 to SEG60 V1 ,V2,V3,V4,V5
VDD Status
RES
LCD drive circuit
Common counter
Display data latch circuit
Display start line register
Line address decoder
Line counter
Display data RAM (2560-bit)
Column address decoder
CL FR
Column address register
MPU interface
D0-D7
A0,CS
BLOCK DIAGRAM IZD1520OA
2
RD,RW (E,RW) M/S
Bus holder
Command decoder
Low-address register
Display timing generator circuit
Column address counter
I/O buffer
VSS
IZD1520U
COM0 to COM15 SEG0 to SEG60 V1 ,V2,V3,V4,V5 VDD Status
RES
LCD drive circuit
Common counter
Display data latch circuit
Display start line register
Line address decoder
Line counter
Display data RAM (2560-bit)
Column address decoder
OSC2 FR
Column address register
MPU interface
D0-D7
OSC1
3
RD,RW (E,RW) M/S
Bus holder
Command decoder
Low-address register
Display timing generator circuit
Column address counter
I/O buffer
VSS
IZD1520U
BLOCK DIAGRAM IZD1521AA, IZD1521OA
SEG0 to SEG79
V2,V3,V5
VDD Status
RD,RW (E,RW) RES
LCD drive circuit
Display data latch circuit
Display start line register
Line address decoder
Line counter
Display data RAM (2560-bit)
Column address decoder
CL FR
Column address register
MPU interface
D0 -D7
ELECTRICAL CHARACTERISTICS (Ta = 25oC, VDD = 0V, VSS = -5.0V unless otherwise specified) 4
A0,CS
Bus holder
Command decoder
Low-address register
Display timing generator circuit
Column address counter
I/O buffer
VSS
IZD1520U
Characteristic Operating Voltage(1) Note 1 Recommended Operating Voltage(2) Permitted Permitted HIGH Input Voltage V1, V2 V3, V4 VIH V1, V2 V3, V4 A0,Di, E, R/W, CS CL, FR, M/S, RES LOW Input Voltage VIL IOH = -3.0 mA HIGH Output Voltage VOH IOH = -2.0 mA IOH = -120 A IOL = 3.0 mA LOW Output Voltage Input Leakage Current Output Leakage Current LCD Driver ON Resistance Note 2 Supply Current, Static IDDQ CS = CL = VDD During display V5=-5.0V Supply Current, Dynamic IDD fCL=2kHz Note 3 Rf =1M Note 4 fCL=18KHz Note 5 During access fcyc=200KHz f = 1 MHz Rf =1M2% RES 5.0 300 All inputs 15 1.0 5.0 18 10.0 500 8.0 21 1000 A pF KHz s VDD VOL ILI ILO RON Outputs are high impedance V5=-5.0V IOL = 2.0 mA IOL = 120A A0, Di, E, R/W, CS CL, FR, M/S, RES D0 / D7 FR OSC2 D0 / D7 FR OSC2 A0, E, R/W, CS, CL, M/S, RES D0 / D7, FR SEG0 ~ SEG79 COM0 ~ COM15 VDD 0.05 2.0 9.5 1.0 5.0 15.0 A A -1.0 -3.0 5.0 V5 V5 -13.0 -13.0 0.6 x V5 V5 VSS+2.0 0.2 x VSS VSS VSS VSS+2.4 VSS+2.4 0.2 x VSS VSS+0.4 VSS+0.4 0.8xVSS 1.0 3.0 7.5 A A K V V VDD 0.4xV5 VDD VDD VSS+0.8 0.8+VSS V V -3.5 V Recommended VSS VSS Symbol Test Condition Applicable Terminals Min -5.5 -7.0 Typ -5.0 Max -4.5 -2.4 V Unit
Input Terminal Capacity Oscillator Frequency Reset Time
Notes: 1.
CIN fOSC tR
Operating over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during CPU access. 2. For a voltage differential of 0.1V between input (V1, ..., V4) and output (COM, SEC) pins. All voltages within specified operating voltage range. 3. IZ1520AA and IZ1521AA only. Does not include transient currents due to stray and panel capacitances. 4. IZ1521OA only. Does not include transient currents due to stray and panel capacitances. 5. IZ1520OA only. Does not include transient currents due to stray and panel capacitances.
5
IZD1520U
* Read/Write timing for the 80-port MPU
Characteristic Address hold time Address setup time System cycle time Control pulse width Data setup time Data hold time VDD access time Output Disable time Low-level pulsewidth High-level pulsewidth Rise time Fall time FR delay time FR delay time Note 1 Note 2 Symbol tAH8 tAW8 tCYC8 tCC8 tDS8 tDH8 tACC8 tOH8 tWLCL tWHCL tr tf tFDR tFDR FR (Input) FR (Input) -2.0 CL D0 / D7 CL = 100pF 10 35 35 30 30 0.2 0.2 150 150 2.0 2.0 WR, RD Signal A0, CS Condition Min 10 20 1000 200 80 10 90 60 Typ Max Unit ns ns ns ns ns ns ns ns s s ns ns s s
* Read/Write timing for the 68-port MPU
Characteristic System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulse width READ WRITE tWLCL tWHCL tr tf Note 1 Note 2 tFDR tFDR FR (Input) FR (Input) -2.0 CL Symbol tCYC6 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 tEW E D0 / D7 CL = 100pF 100 80 35 35 30 30 0.2 0.2 150 150 2.0 2.0 Signal A0 R/W Condition Min 1000 20 10 80 10 10 60 90 Typ Max Unit ns ns ns ns ns ns ns ns ns s s ns ns s s
Low-level pulsewidth High-level pulsewidth Rise time Fall time FR delay time FR delay time
* The rating when VSS = -3.0V are approximately 100% higher that when VSS = -5.0V Notes: 1. The listed input tFDR applies to IZ1520 and IZ1521 in slave mode. 2. The listed input tFDR applies to IZ1520 and IZ1521 in master mode.
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IZD1520U
* TIMING CHART * Read/Write timing for the 80-port MPU
AO, CS tAH8
WR, RD
tAW8
tCC8
tCYC8
tDS8 D0~D7 (WRITE) tACC8 D0~D7 (READ)
tDH8
tOH8
* Read/Write timing for the 68-port MPU
* Read/Write timing for the 80-port/68-port display
CL tWHCL tWLCL tDFR tf tr
FR
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IZD1520U
TERMINAL DESCRIPTION
Terminal Name D0 / D7 A0 Data I/O Select display data or functions. HIGH: Display data LOW : Instructions Resets the system and selects the interface type for a 68-port/80-port MPU RES CS OSC1 E (RD) R/W (WR) CL OSC2 FR SEGn COMn M/S VDD VSS V1, V2, V3, V4, V5 HIGH: 68-port MPU interface LOW : 80-port MPU interface Input. Active low. Effective for an external clock operation model only. Chip Select input LOW : Active level sensing Read/Write Enable signal when a 68-port MPU is connected. (Active LOW Read Enable signal when an 80-port MPU is connected) Read/Write Select signal when a 68-port MPU is connected. HIGH: Read Select LOW : Write Select (Active LOW Write Enable input when an 80-port MPU is connected Rising edge sensing) Input. Effective for an external clock operation model only. External clock input (only effective with external clock types) LCD Frame (AC- conversion) signal input/output Segment output for driving the LCD Common output for driving the LCD Master/Slave Select signal 5V power supply 0V power supply (GND level) Power supplies for driving the LCD. VDD V1 V2 V3 V4 V5 Function
8
IZD1520U
DISPLAY COMMANDS (Based on the 80-port MPU; the RD and WR commands differ for the 68-port MPU)
Command 1 Display ON/OFF
RD WR A0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 1 0/1
Function Switches the entire display ON or OFF regardless of the Display RAM's data or the internal status. *Note Determines the line of RAM data to be displayed at the display's top line (COM0) Sets the page of the Display RAM in the page address register Sets the column address of the Display RAM in the column address register Reads the status. BUSY 1: Busy (internal processing) 0: READY status ADC 1: Rightward (forward) output 0: Leftward (reverse) output ON/OFF 1: Display OFF RESET 1: Resetting 0: Display ON 0: Normal
2 3 4
Display START Line Page Address Set Column (Segment) Address Set Status Read
1 1 1
0 0 0
0 0 0
1 1 0
1 0
0 1
Display START address (0 / 31) 1 1 0 Page
Column address (0 / 79)
5
0
1
0
0
0
0
0
6
Write Display Data Read Display Data
1
0
1
Write Data
Writes the data on These commands acthe data bus to RAM cess a previously specified address Reads data from the of the Display RAM, Display RAM onto after which the column the data bus address is incremented one
0 0 0 0 0/1
7
0
1
1
Read Data
8
ADC Select
1
0
0
1
0
1
Used to reverse the correspondence between the Display RAM's column addresses and segment driver output ports 0: Rightward (forward) output 1: Leftward (reverse)
9
Static Drive ON/OFF
1
0
0
1
0
1
0
0
1
0
0/1
Selects normal display operation or static all-fit drive display operation 1: Static drive (Power Save) 0: Normal display Selects the duty factor for driving LCD cells 1: 1/32 duty 0: 1/16 duty Increments the column address counter by one only when display data is written but not when it is read Cancels the Ready Modify Write mode Resets the Display START line to the 1-st line in the register. Resets the column address counter and page address register to 0.
10 Duty Select 11 Read Modify Write 12 End 13 Reset
1 1
0 0
0 0
1 1
0 1
1 1
0 0
1 0
0 0
0 0
0/1 0
1 1
0 0
0 0
1 1
1 1
1 1
0 0
1 0
1 0
1 1
0 0
Note: Power Save mode is entered by selecting static drive in the Display OFF status.
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IZD1520U
REFERENCE CIRCUITRY EXAMPLES * 16 x 141 dots * 16 x 61 dots
1/16 duty
1 16 LCD Cell 16 x 61 dots 1 - 61 SEG
1/16 duty 1 16 1 - 61 SEG LCD Cell 16 x 141 dots
62 - 141 SEG
COM
COM
VDD
VDD M/S M/S
M/S
D
A0
OSC1
OSC2
D
A0 OSC1 OSC2 FR
FR
CL
A0
D
MPU CB DB A0
Rf
MPU CB DB A0
Rf
* 32 x 202 dots
1/32 Duty 1 16 LCD Cell 32 x 202 dots 1 - 16 SEG 62-141 SEG 142 - 202 SEG 17 32
COM
COM
VDD M/S A0 OSC1 OSC2 FR FR D CL M/S M/S
D
A0
FR
D
A0
CL
FR
MPU CB DB A0
Note: If a system has two or more slave drivers a CMOS buffer will be required for clock signal.
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IZD1520U
PAD LAYOUT
80 81 82 83 84 85 86 87 88 89 90 (0,0) 91 92 93 94 95 96 97 98 99 100
X
(6500, 5000)
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50 49 48 47 46 45 44 43 42 41 40
Y
PAD DIAGRAM BT1520 Chip size : 6500 x 5000 Pad size : 120 x 120 Unit : m
39 38 37 36 35 34 33 32 31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PAD LOCATION ( Unit: m)
Pad No. Pad Name X Y Pad No. Pad Name X Y Pad No. Pad Name X Y 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 1895 1695 1497 1297 1097 916 737 542 342 162 -18 -198 -398 -603 -806 -996 -1166 -1375 -1544 -1753 1 COM5 -2994 -2243 35 SEG37 3010 -1100 69 SEG3 -650 2 COM6 -2717 -2244 36 SEG36 3010 -892 70 SEG2 -798 3 COM7 -2510 -2244 37 SEG35 3010 -722 71 SEG1 -968 4 COM8 -2302 -2244 38 SEG34 3010 -515 72 SEG0 -1177 5 COM9 -2132 -2244 39 SEG33 3010 -344 73 A0 -1368 6 COM10 -1924 -2244 40 SEG32 3010 -136 74 OSC1 [CS] -1569 7 COM11 -1754 -2244 41 SEG31 3010 33 75 OSC2 [CL] -1761 8 COM12 -1547 -2244 42 SEG30 3010 241 76 E [RD] -1953 9 COM13 -1377 -2244 43 SEG29 3010 412 77 R/W (WR) -2142 10 COM14 -1167 -2244 44 SEG28 3010 620 78 GND -2348 11 COM15 -998 -2244 45 SEG27 3010 790 79 DB0 -2646 12 SEG60 -790 -2244 46 SEG26 3010 998 80 DB1 -3009 13 SEG59 -620 -2244 47 SEG25 3010 1170 81 DB2 -3009 14 SEG58 -413 -2244 48 SEG24 3010 1376 82 DB3 -3009 15 SEG57 -242 -2244 49 SEG23 3010 1544 83 DB4 -3009 16 SEG56 -35 -2244 50 SEG22 3010 1754 84 DB5 -3009 17 SEG55 135 -2244 51 SEG21 3010 2242 85 DB6 -3009 18 SEG54 344 -2244 52 SEG20 1494 2242 86 DB7 -3009 19 SEG53 514 -2244 53 SEG19 2434 2242 87 VCC -3009 20 SEG52 722 -2244 54 SEG18 2226 2242 88 RES -3009 21 SEG51 892 -2244 55 SEG17 2056 2242 89 FR -3009 22 SEG50 1100 -2244 56 SEG16 1848 2242 90 V5 -3009 23 SEG49 1270 -2244 57 SEG15 1678 2242 91 V3 -3009 24 SEG48 1478 -2244 58 SEG14 1470 2242 92 V2 -3009 25 SEG47 1607 -2244 59 SEG13 1300 2242 93 M/S -3009 26 SEG46 1856 -2244 60 SEG12 1012 2242 94 V4 -3009 27 SEG45 2026 -2244 61 SEG11 922 2242 95 V1 -3009 28 SEG44 2234 -2244 62 SEG10 714 2242 96 COM0 -2994 29 SEG43 2477 -2244 63 SEG9 544 2242 97 COM1 -2994 30 SEG42 3020 -2244 64 SEG8 336 2242 98 COM2 -2994 31 SEG41 3010 -1857 65 SEG7 166 2242 99 COM3 -2994 32 SEG40 3010 -1648 66 SEG6 -42 2242 100 COM4 -2994 33 SEG39 3010 -1474 67 SEG5 -213 2242 34 SEG38 3010 -1270 68 SEG4 -420 2242 Note: Pads 74,75 are OSC1, OSC2 for BT5150OA and CS, CL for IZ1520AA respectively. All other pad names are identical.
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IZD1520U
PAD LAYOUT
80 81 82 83 84 85 86 87 88 89 90 (0,0) 91 92 93 94 95 96 97 98 99 100
X
(6500, 5000)
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50 49 48 47 46 45 44 43 42 41 40
Y
PAD DIAGRAM BT1521 Chip size : 6500 x 5000 Pad size : 120 x 120 Unit : m
39 38 37 36 35 34 33 32 31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PAD LOCATION ( Unit: m)
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 X -2994 -2717 -2510 -2302 -2132 -1924 -1754 -1547 -1377 -1167 -998 -790 -620 -413 -242 -35 135 344 514 722 892 1100 1270 1478 1607 1856 2026 2234 2477 3020 3010 3010 3010 3010 Y -2243 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -2244 -1857 -1648 -1474 -1270 Pad No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pad Name SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 X 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 3010 1494 2434 2226 2056 1848 1678 1470 1300 1012 922 714 544 336 166 -42 -213 -420 Y -1100 -892 -722 -515 -344 -136 33 241 412 620 790 998 1170 1376 1544 1754 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 Pad No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name SEG3 SEG2 SEG1 SEG0 A0 CS CL E RD R/W (WR) GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCC RES FR V5 V3 V2 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 X -650 -798 -968 -1177 -1368 -1569 -1761 -1953 -2142 -2348 -2646 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -3009 -2994 -2994 -2994 -2994 -2994 Y 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 2242 1895 1695 1497 1297 1097 916 737 542 342 162 -18 -198 -398 -603 -806 -996 -1166 -1375 -1544 -1753
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